IBM SP World 97 user event

The main attraction was a presentation on the US government ASCI programme, given by Randy Christensen, which specified the delivery of 1 Teraflops sustained performance by 1998. The IBM system is at Lawrence Livermore Laboratories and with a 512 Node SP system has a peak performance of 3 Teraflops.

About 400 people attended - about 1/3rd scientist/engineers from Europe. The most interesting IBM pitch was a talk on ASCI, by Randy Christensen, emphasising US government commitment to this technology and huge investment in re-writing all applicaitons for Teraflops HPC. They aim to have all applications scalable for message passing.

There were a few IBM presentations on future products/directions that were also interesting. These included presentations on the 64-bit arithmetic new IBM RS/6000/397 processor and how it dovetails with the 32-bit past across all IBM systems. In commercial systems these are available as either new systems or as upgrades to existing RS/6000 servers.

The RS6000/397 SP chip has a relatively low speed, (160 MHz), but is a well balanced chip delivering around 30% sustained performance. This is achieved because of its 2.6GB/sec memory bandwidth and its ability to perform 6 instructions per cycle. It is very good at floating point numbers rather than integers. The IBM RS6000/397 chip in an SP HPC system is a formidable machine and this is reflected in the fact that of the Top 500 systems 126 are IBM RS6000 SP based.

New nodes for RS/6000 SP, the massively parallel system which is the basis for IBM Big Blue Chess Grand Master machine and the processors used in the ASCI programme, will incorporate the RS6000/397 chip, supported by AIX4.3, the IBM version of the UNIX Operating System which supports the 64-bit arithmetic of the new hardware.