Compaq new clustered supercomputer AlphaServer SC series

Munich 02 Dec 99 In a Munich press meeting Compaq announced its new business strategy and the AlphaServer SC series, a Teraflop cluster of SMP servers connect via a high-speed Quadrics interconnect. Actually the top system which is delivered - and will be finalised by end of 1999 - to the Lawrence Livermore National Lab. as part of the the ASCI PATH FORWARD Program will have a peak performance of .7 TFlop/s. Compaq disclosed its further development plans in Alpha processor as well as in the SC series.

Heinz Schepers, Director ESSG, presented the new organisation which is divided in Enterprise Solutions and Services Group (ESSG), the Commercial Personal Computer Group and the Consumer Group. Sales, logistics, e-Commerce and quality assurance cross all these groups. He gave a specific view on the non-stop server. Their target markets are service provider, telco, finance, manufacturing and HPTC - high-performance technical computing. These markets are interesting for the new SC series too.

Dr. Harald Meier-Fritsch, HPTC Germany at Compaq, demonstrated the performance of the Alpha processor by looking at the Top500 list, the percentage of CPUs, GFlops and sites - represented by T3Es. Then he disclosed the Alpha roadmap, the EV67 this year in .25 micron technology, 700 - 800 MHz clock rate and 15 M transistors on a chip. Next year EV68 will appear with .18 micron and 800 - 1000 MHz. Critical with high clock rates is the memory access time. The Alpha can execute out-of-order, this hides latency. While EV56 had a sustained memory bandwidth of about 350 MB/s, EV6 is improved to about 2 GB/s and EV7 to 10 GB/s. Furtheron the L2 cache is extended up to 8 MB. EV7 integrates L2 cache and SMP communication by four 6.4 GB/s channels. Thus a 2-D torus can easily be build. 64 cpus can be collected in one system. EV8 improves the usage of the clock cycles by SMT, simultaneous multithreading. Up to 4 threads can be processed in parallel. EV8 is a single chip SMP.

Alpha SMP Server

ES40 is the new system and the building block of the SC series and will be shipped in 1.Q 2000 with Alpha EV67. Four CPUs are connected via a crossbar with the memory of up to 32 GB SDRAM with 4 MB/s per CPU. The clock rate is 667 MHz which results in a peak performance 1.33 GFlop/s. SPECint95 is 38.3, SPECfp95 is 82.2.

Compaq AlphaServer SC Series (Codename Sierra)

Following Dr. Martin Walker, Compaq succeeded within 6 months to go from a prototype towards a full scale product. He expects markets for the SC in new-product development, research, defense/security/energy, weather forecasting and climate modelling and financial services. The basic architecture is based on high-end SMP processing elements (4-32 CPUs), multiple rails of scalable switch interconnect (> 200 MB/s per rail, about 5 micro seconds MPI latency) and a system software for single system management. The system is built from standard components, actually ES40 SMPs, QSW (Quadrics Supercomputers World) SC interconnect, Tru64 Unix, cluster file system and system administration software, QSW parallel file system and resource management software and a parallel application development environment and tool from Compaq and ISVs. Walker expects beneath the Alpha improvements and new building blocks as the GS SMP series and the interconnect improves, going from 16 nodes 200 MB/s to 128 nodes 500 MB/s, 256 nodes 1 GB/s, ... The interconnect is based on Elan-3 PCI adapter, DMA driven, get and pull and 200 MB/s per rail bi-directional.The Elite ist a fat tree switch, 8-way x-bar switch, 16 or 128 port package and 35 nano seconds latency. The MPI performance is 5.1 micro seconds ping-pong latency. The switch has 200+ MB ping-pong bandwidth using 64 KByte messages. Half of the performance (n1/2) is reached with 2500 Bytes messages. The prototye Sierra was constructed in April 1999, the factory integration of the first customer configuration was in August and the installation of the cluster was in September at Lawrence Livermore Lab. It consists of 128 ES40 nodes with 512 processors. The system ranked 34 in the current Top500 list with 271.4 GFlop/s Rmax and 512 GFlop/s peak contains the "old" EV6 500 MHz processor. For software development, Compaq offers the F95, C, C++, Java and other compilers, OpenMP for shared memory, Shmem for T3E users, MPI (MPI 2, MPI-I/O, thread-safe), 3rd party software as TotalView debugger, Vampir for performance analysis and batch queue management LSF and GRD.

SC Roadmap

Walker presented the TFlop/s roadmap


year	Alpha MHz	nr SMP CPUs	 nr nodes	TFlop/s

1999	667		4		128		.7

2000	>800		32		128		~ 7

2001	>1000		64		256		~30

2002	>1200		64		256		~40

2004	~1500		64		256		~100

Drazen Stilinovic, Vice President QSW, gave an overview of the history and the cooperation with Compaq. QSW is part of the FINMECCANICA Group and exploits the Meiko - CS2 - technology. The AlphaServer SC is a qualified system with guaranteed function. In the partnership QSW provides interconnect and enabling management software, Compaq provides AlphaServer roadmap, manufacturing, software and support. QSW's future will be a high-availability strategy for QsNet III, the scalability up to 1000s of nodes and development of QsNet IV and beyond. The business model is based on providing core technology to the SC series, reselling SC series in Europe and providing SC consultancy services toi European customers.

SC Shipments

The first systems have been shipped to Lawrence Livermore Nat. Lab (LLNL) and the first machine in Europe was shipped to the civilian department of the French Atomic Energy Commission (CEA-Civil). LLNL will have two 512 (4x128) 667-MHz-processor systems which will be connected and then being the most powerful Alpha system ever built.

www.compaq.com/hpc

Uwe Harms

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