New model boosts NEC SX-5 performance to 5 Tflop/sMannheim 0 2000 At the Mannheim supercomputer conference, NEC presented upgrade plans for the current SX-5 supercomputer increasing the maximum overall performance to 5 Tflop/s. The clock cycle of the SX-5 will change from 250 MHz to 312.5 MHz. There are also improvements to the vector processor.
A 25% increase in clock speed of the NEC SX-5 system and improvements in the vector processor will lead to a performance improvement
for real applications of 20-40%. The first new enhanced SX-5 models will be available Autumn this year.
The clock cycle of the SX-5 will change from 250 MHz to 312.5 MHz. This will result in an immediate increase in both
vector peak performance and scalar peak performance. Scalar performance per CPU will go up to an impressive 625 Mflop/s. Vector speed per
processor will reach the 10 Gflop/s mark. Per node the vector processing performance will go up to
160 Gflop/s and the overall system performance for the high-end model will reach 5 Tflop/s.
Apart from the improvement in cycle time, also the architecture of the vector processor will be enhanced in several ways.
The maximum vector length, currently 256, will go up to 512. The vector register capacity will be enlarged to
288 Kbyte. This will increase the sustained speed for applications that can make use of long vectors.
In general all vector intensive applications will benefit.
The new SX-5 model line up will consist of 5 basic models: the S-model (up to 8 Glop/s), the D-model (up to 20 Gflop/s),
the C-model (up to 40 Gflop/s), the B-model (up to 80 Gflop/s) and the A-model (up to 160 Gflop/s).
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