The state of the industry: all the vendors presented in MannheimMannheim 10 jun 2000 As much as 19 vendors, hardware, software, middleware, networking and storage presented their actual products. The highlights are listed here. From SuSe presenting their cluster Linux to Burton Smith painting the future of Cray Inc. from Qompaq presenting their latest supercomputer to Pallas presenting a new code-coupling packages.
Herbert Cornelius disclosed some figures from IA64, 800 MHz clock, 20 operations/clock, 3.2 GFlop/s 64-bit and 6.4 GFlop/s 32-bit peak performance. 1- 4 way SMPs are planned, the Intel SHV 460V chipset will be used. Alberto Guglielmi preseted their netwotk independent SAN (System Area Network) solution. There is the possibility to bypass the operating system. It then can be thought as an extension of direct memory access to the network. A transaction based protocol for high bandwidth and low latency was defined. Wolfgang Dreyer discussed his offering in the Linux cluster world. He uses own software and the ParaStation in connection with Myrinet to build clusters out of Compaq'a Alpha processors from 32 to 256 nodes.
Karl Solchenbach discussed the new trend in scientific computing, the coupling of different application codes in the scientific simulation. A data exchange between CFX, StarCD, Fluent, MSC's Nastran and Marc, Permas, Ansys and PamCrash is possible. The file can be downloaded from www.mpcci.org.
Lawrence Mulholland presented some features of the actual NAG library for parallel machines.
Wolfgang Gentzsch, now leaving for America as CTO of Gridware, commented the integration of Genias, Regensburg, Germany, and Chord, the largest LSF distributor, to the new company Gridware. The headquarter will be in California with marketing, sales etc., the further development and improvement will be located in Neutraubling near Regensburg. Their goal is that Codine/GRD will become world standard in resource management systems.
After Coffee Break another hard to listen part followed, 150 minutes permanent information. This more hardware oriented part will be shortly summarised. Jamshed Mirza first discussed IBM's achievments in the ASCI project and discussed IBM's ASCI White proposal, 12 TFlop/s peak, 512 nodes consisting of 16.way Power 3 SMPs, 24 GF/s and up to 32 GB memory per node. The Power 4 will have 1 + GHz clock and is a single design for technocal and commercial market. The processor is on power since January 2000 and is operating at 1 GHz. AIX was booted on the SMP operational. IBM wants to build a Linux cluster infrastructure, ISVs are interested. Jochen Krebs discussed the CEA 5 TFlop/s machine in France for nuclear weapon simulation. The initial version will have 35 GFlop/s, an intermediate 500 GFlop/s in 2001 whch will be extended to 1 TFlop/s the same year. The final machine should have 1 TFlop/s sustained. The Alpha processor's roadmap: Eric Schnepf described their offering, the hpcLine based on Pentium III got a good acceptance in academia, research but also in industry. A lot of program packages like CFX, FEKO, FIRE, Fluent and Magma are running, the company is indiscussion with McNeal Schwendler Nastran and Marc and StarCD for porting. The other is the vector computer VPP5000, about 100 processors sold in Europe. The performance improvements comparing the VPP300E and VPP5000 are greater than the clock improvements. Because of the marriage, the Fujitus GP7000F is in the portfolio too, now namend Primepower, a 128 way SMP based on SPARC architecture and delivering 3 floating point operations per clock. Tim Lanfear described the different SR8000 models, entry level systems with 4/8/12 GFlop/s. He additionally showed the specific architectural features like pre loading and pre fetching. It is Hitachi developed RISC processor but uses the IBM Power PC instruction set.
Frank Baetke mentioned the PA 8700 with a peak performance of more than 3 GFlop/s. In total 4000 V-classes have been shipped. HP sees different market segments, clustering different machines via Hyperplex or a close connection of actually 32 way SMPs. End of this year HP will announce the successor of the V-class. The IA64 runs HP-UX native.
Burton Smith presented the new formed company, 900 employees includin 400 engineers, 600 systems in 32 countries. Their portfolio:
Cray T3E with up to 2048 processors, in Q4 2000 the T3E 1350 with the 675 MHz Alpha will be announced.
SV1e 400 MHz version since 1Q 2000.
MTA all CMOS MTA2 is produced in second half of 2001, up to 256 processors, 1 TByte uniform flat shared memory. SV2 vector meets T3E style, produced in 1. half 2002, 1024 nodes of 50 GFlop/s and 32, later 64, GB memory.
Burton Smith proposed in addition to the Linpack a new benchmark, which measures and needs the bisectional bandwidth, e.g. an iterative sparse solver.
Wolfgang Mertz mentioned new processors and presented the SN1 which can be seen as the SGI 3000. Their specifics, a ccNUMA method with more than 1000 processors. Folowing Mertz, SGI is committed to HPC and high-end graphics and will continue its cooperation with customers and software vendors.
Wolfgang Kroj presented some infos about the UltraSPARC III with interval arithmetic and shared memory cluster systems. More than 2500 E10000, 250 in Germany, have been sold. The new server hardware will be compatible with the old.
Quadrics cooperates with Compaq and delivers a fast interconnect and the resource management system for the Alpha cluster. It has a single system image. The company sold Alpha SC in UK (5 systems) and Italy (1 syst.). It has a partnership with API. It will add high-availability features to its software.
Uwe Harms |
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