Breakthrough in chip design allows 4.5 Ghz for future chips
San Franscisco 07 Feb 00 IBM Research announced breakthrough results in developing a new family of experimental high-speed computer circuits that run at test speeds up to five times faster than today's top chips.The new circuits employ an innovative design -- called "Interlocked Pipelined CMOS" , to reach speeds of 3.3 - 4.5 billion cycles per second (3.3 - 4.5 GHz), using conventional silicon transistors, while dramatically reducing power consumption. IBM researchers estimate that chips made with IPCMOS circuits would require only half the power used by a standard high-performance chip.
"To meet continuing demand for performance, we're going to have to look beyond simply making circuits smaller," said Dr. Randall D. Isaac, vice president, Systems, Technology, and Science, IBM Research. "Increasingly, performance gains will be driven by innovations in chip design. With breakthroughs such as our silicon-on-insulator technology moving into the market, and new circuit architectures and promising research like IPCMOS under way in our labs, IBM is building its arsenal for the era of multi-gigahertz chips."
The key to the IPCMOS design is a distributed "clock" function. In computer chips, the clock paces the speed of the circuits. Standard designs use a centralized clock to synchronize the operations of an entire chip, ensuring that all operations run at the same interval, or cycle. The clock waits for all the operations on a chip to finish before starting the next cycle, so the speed of the entire chip is limited to the pace of the slowest operation. To increase the speed, the IBM researchers decentralized the clock, using locally generated clocks to run smaller sections of circuits. This locally generated clock has two significant advantages:
- Speed: Faster sections of circuits are free to run at higher cycles without needing to wait for slower operations to catch up.
- Power: The distributed IPCMOS clocks send signals locally only when an operation is being performed, significantly reducing power requirements. Centralized clocks send a signal to the entire chip, and the synchronizing function can use as much as 2/3 of the total power consumed.
"Maintaining a synchronous clock across an entire chip becomes increasingly difficult as performance rises, and the clock itself can limit performance," said Stanley Schuster, one of the researchers working on IPCMOS. "We believe this new design will help us overcome those problems in future generations of high-speed chips."
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