Fujitsu introduces a VLIW based processor

Designed for System-on-Chip implementations, the FR-V architecture provides designers with a varied set of configuration options.

The first core to be released, the High-Performance FR500, executes 4 instructions simultaneously, and is based on the Very Long Instruction Word (VLIW) concept developed by Fujitsu.

The core consists of 32-bit Integer instruction sets, and floating point and media instruction sets. In total these amount to six execution units. Two x 32-bit integer execution units; two x floating point execution units and two x media execution units. Each of the media and floating point units is joined to form one slot, and combined with two independent Integer units, a total of four slots is reached.

The FR500 reads the instruction packets for these slots and executes the 4 instructions simultaneously in parallel. Because of the high performance, functions traditionally performed in hardware can be executed by software.

Designed using 0.18 micron technology, the first device, the MB93501, operates at a frequency of 266MHz, with a peak performance of 1064 MIPS (million instructions per second) integer processing, 4256 MOPS (million operations per second) application processing and 1064 MFLOPS (million floating point operations per second). It is housed in a 352 BGA package, and has a die size of 7 x 7mm. A power consumption of just 1W for the core is required.

The FR500 processor core is targeted at multimedia systems, such as car navigation systems, digital TV applications, and many other applications which need processing for graphics, sound etc. to be executed in parallel.

Fujitsu offers a software development system, a Development Debugging Tool, with the FR-V architecture.

For processing in parallel, both software and compilers need to be powerful. The compiler has to be able to put instructions together in the correct way so they go into the appropriate slots. Development environments of the new processor core are based on an advanced version of a vector compiler used in Fujitsu supercomputers .

The FR500 compiler packs the four 32-bit long instructions into a 128-bit long VLIW. A "packing flag-bit" is also incorporated in each 32-bit instruction to eliminate "No Operations," which would degrade the performance and increase the memory size.

Packed VLIW instructions can be placed on memory without increasing instruction memory size. The processor core of the FR500 fetches the packed instruction using instruction cache and unpacks it to configure a four 32-bit instruction VLIW.

It is planned that a smaller device, the low power FR300, will be released towards the end of the year, containing just Integer and DSP instruction sets. This will be targeted at mobile phone markets.