Mercury and Motorola develop high-performance embedded interconnect

In addition to larger embedded markets such as networking and wireless communications, high-performance digital signal and image processing applications should especially benefit from RapidIO's increased connectivity and throughput. These applications include digital video broadcasting, medical diagnostic imaging, radar, sonar, signals intelligence, and semiconductor wafer inspection. The expected broad adoption and availability of RapidIO interfaces means that companies can take advantage of a standard specification and off-the-shelf components instead of developing proprietary solutions.

"Next-generation products for wireless base stations and digital video broadcasting systems will require substantially higher bandwidth and connectivity than today's systems allow," said Jay Bertelli, president and CEO of Mercury Computer Systems. "Today's highest-performing multiprocessing systems gain much of their speed from the switched-fabric chips and boards inside them. RapidIO can put this power in a tiny corner of a single chip. We look forward to working with other technology leaders to help adopt its benefits for a broader market."

"The RapidIO interconnect architecture will play a crucial role in areas that require increased bandwidth and processing power, such as networking and wireless communications infrastructures," said Daniel Artusi, corporate vice president and general manager of Motorola's Networking and Computing Systems Group. "This architecture is the answer to the increasing demand for throughput on the most popular integrated communications processors, host processors, and networking digital signal processors."

The RapidIO Trade Association will maintain and promote the interconnect standard. Initial members will include telecommunications/networking companies, manufacturers and vendors of processors and interface products, and systems providers. Other interested parties are invited to join. RapidIO Technology Background

The RapidIO interconnect enables chip-to-chip and board-to-board communications at performance levels that scale from over a gigabyte per second per port to an aggregate of hundreds of gigabytes per second in a single system. Unlike system-to-system protocols, RapidIO provides both the high bandwidth and low latency required for intra-system communications. The RapidIO interconnect is designed to fit inside a field programmable gate array (FPGA) with room to spare for additional functionality. The combination of performance, ease of use, and small silicon footprint paves the path for this new standard switched-fabric architecture to augment the traditional system bus in embedded systems.