Synopsys' Physical Synthesis is used by Cray to tape out eight million-Gate, 450 Mhz, 1.8 Gflop/s Vector CPU ASIC for new SV1eMountain View 07 Nov 2000 Synopsys announced that Cray has successfully taped out an eight million-gate, 450 MHz, vector processor ASIC using Synopsys' Physical Compiler. The design was implemented using a copper-based 0.12-micron process technology. The chip, code named Processor Vector Cache (PVC), is being used in the new Cray SV1e scalable-vector supercomputer, which was announced today at the IEEE Supercomputing 2000 conference in Dallas, Texas.
Cray incorporated Physical Compiler into its ASIC flow as a CAD tool enhancement
to achieve aggressive SV1e project objectives. Cray was able to use Physical
Compiler with less than a week of startup effort, by leveraging its current
Design Compiler infrastructure. With Physical Compiler central to their
timing-closure flow, Cray achieved their very aggressive circuit performance
goals while saving significant design time.
Pioneered by Synopsys, Physical Synthesis helps designers address the
implementation challenges of next-generation system-on-chip designs. Physical
Synthesis brings key physical design considerations forward in the design flow,
allowing RTL designers to rapidly achieve high quality of results. The overall
design flow includes Chip Architect design planner, Physical Compiler unified
synthesis and placement, and FlexRoute top-level router. Synopsys' Physical
Synthesis leverages industry-standard tools such as Design Compiler, Module
Compiler and PrimeTime(R) and its proven interfaces to third-party solutions
allow it to easily plug into an existing design flow.
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