SC2000 Keynote - Towards Petaflop/sUtrecht 30 November 2000 This year's keynote address was delivered by Steve Wallach, a supercomputing veteran, co-founder of Convex and for long years CTO for High Performance Computing at Hewlett Packard when it took over Convex. He is now a venture capitalist acting in the HPC field.
Wallach addressed in his talk ``Petaflops in the Year 2009'' what he
called ``ASCI Standard'' systems, i.e., systems with > 8192 nodes
and costing around US$ 150 million. According to the Semiconductor Industry
Alliance (SIA) surveys in 2008 the intra-chip cycle will be increased to
6 GHz while inter-chip frequency will have gone to 2.5 GHz. The
existence of Petaflop systems by the year 2009 will critically depend on
the availability of sufficiently fast networks. In this respect the
future seems promising. Optical switching at 40 GHz (OC768) will be
investigated in the next year and All Optical Networks (AONs) seem,
thanks to recent breakthroughs, a viable option within the timeframe
considered by the speaker. So, in his opinion the structure of a
Petaflop system would feauture 8192 4-CPU dies at 6 GHz frequency,
delivering 200 Gflop/s per die. These would be housed in 64-unit racks
where each racks would only draw 30 KWatts. Furthermore, the system
would have a 2-tier main memory; one level on chip and one level
in-rack. Both memories would have the same bandwidth but, of course,
different latencies. The total system with a Theoretical Peak
Performance of 1.6 Pflop/s would be connected by a 128-channel
multi-Lambda AON.
The structure Wallach presented is in many respects reminiscent to the
HTMT architecture described by Thomas Sterling. However, the latter
system sadly never will be built because of an unfortunate cut of funds
for this project.
Petaflop systems in different contexts were a recurring theme throughout
the conference in various panels on which we will comment later.
Aad van der Steen |
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