NEC's Supercomputer Road MapHeidelberg 23 jun 2001 At SC2001 in Heidelberg, Dr. Joerg Stadler, Marketing Manager, NEC European Supercomputers Systems, presented the NEC Supercomputer Road Map for the next four years. The bottom line message is that NEC is committed to both the vector highly integrated capability systems, the NEC SX5 series, and the scalable capacity servers using the Intel Itanium IA-64 chip set and its successors, McKinley and Madison. Stadler described some interesting developments in the pipe line for both streams and then went on to explain the recent agreement licensing Cray to sell NEC SX systems with exclusive rights for sales in the U.S.A. (author: Chris Lazou).
Heidelberg - Germany, June 21-23: The SC2001 conference was appropriately held in Heidelberg, a beautiful romantic city, but also renown for its radical ideas, often pushing them to success at enormous risk. One which comes to mind is of course Martin Luther's break with the Roman Catholic church in the early 16th century.
Dr. Joerg Stadler, Marketing Manager , NEC European Supercomputers Systems, presented the NEC Supercomputer Road Map for the next four years. Instead of following Luther with his two state (Aristotelian) logic, breaking with one tradition to embrace another, he took a quantum leap and showed that one can take a holistic approach, have both capability supercomputing and capacity scalable servers, with the two product lines accruing mutual benefits.
Stadler went on to explain how NEC perceive the key issues in HPC. One path is the NEC proprietary chip, using high clock frequency, parallel processing with high memory bandwidth, delivering not only peak but high sustained performance. This shared memory vector parallel architecture, is mature, easy to use, reliable and user friendly since the user only has to buy the next version of the hardware to achieve increase in capability. With the incorporation of CMOS technology, the NEC SX5, has benefited from low cost of components and low operational costs.
The current NEC SX5, is an evolutionary product, using a scalable parallel architecture, with a huge shared memory space, and because of its balanced CPU and memory bandwidth throughput, it delivers efficient parallel processing. To give some detail, an SX5 CPU has 16 vector pipes, uses 0.25micron CMOS technology and rated at 8 Gflop/s when using a 4 ns clock. The size of this CPU module is 225X225 mm and needs 32 chips to produce.
NEC have now stated that the SX5 architecture has a future, with a probable announcement of the SX6, before the end of 2001 and two more successor products by year 2004-5. Although one has to wait until the official announcement of the SX6 to evaluate its price/performance merits, what is already known is very promising. It incorporates technology improvements and the whole vector CPU now fits on a chip. This is no mean engineering achievement, since issues like heat extraction and pin numbers needed for out of chip communication, which affect memory bandwidth, cannot be wished away, so the question arises, what are the innovations and engineering trade-of, used to get there.
The exclusion of Japanese Supercomputers from the US market has been extensively reported in PRIMEUR and other publications in the last three years. At the same time the ASCI initiative with its exclusive emphasis on commodity chip technology, had caused the wane of Cray prowess in the vector parallel field, and practically brought the evolutionary path of this architecture, in the US, to its knees. For users such as aerospace, the automotive industry, climate research, and government agencies who have large applications using large sparse matrices, this development was causing concern and loud bells started ringing. For example, the recent Rood report on climate modelling stated, (p20) ...."software challenges are less daunting for tightly integrated vector supercomputers". It went on to say, (p22) ...."the useability of Japanese supercomputers is much higher .... and they are therefore, pragmatically faster".
The message was quickly picked up by top executives of Cray and NEC and translated it into a business opportunity.
NEC and Cray made an agreement effective since May 10th 2001, for Cray Inc., to resell NEC SX5 series and future vector products, as OEM to the US market on an exclusive basis, and non-exclusively world-wide for the
next ten years. The agreement came into effect after US government restrictions have been lifted following an request from Cray. It has the potential for Japanese supercomputer technology to finally come on stream in the US. This levelling of the marketing playing field, is very good news for vector architecture, and non-US NEC customers should benefit from economies-of-scale, as the SX series market is expected to double in the next two years.
The Intel Itanium chip set has been used by many vendors to design their recently announced systems. One of these vendors, NEC has recently announced the AzusA commercial business machine and the Express/5800 Linux variant especially targeted at the scientific and engineering market..
The Express5800 series has an evolutionary path starting with a 4CPUs Itanium processors and extending to 8CPUs and then 16 CPUs. The 16 CPU configuration is available now with 64GB of memory and running 64bit
Linux. The smaller configurations and other operating systems will be available later this year.
In the software area, Windows, Linux and several other operating systems are implemented. For Parallel API, OpenMP and MPI and the usual languages associated with scientific and engineering programming, such as Fortran and C, C++ are to be available on delivery.
Chris Lazou |
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