Siroyan adopts ACE's CoSy compiler development system for next-gen processor

"Our SIP² processor combines RISC, VLIW and DSP elements together with application specific functions, so the compiler needs to be of the highest standard", says Adrian Wise, Siroyan's Technical Director. "Through CoSy's modular architecture, we can achieve optimum performance whilst preserving the robustness of the compilers we construct, giving us better quality products in a shorter time. It's a key factor in our approach to deliver to our customers a professional-quality tool chain comprising compilers, simulation tools and debuggers that are customised to address the target configuration".

"Advanced architectures require a new standard in compiler development", said Rob Kurver, Managing Director of ACE Associated Compiler Experts. "The CoSy system provides developers with an open system that enables the environment to be easily customised to meet the architectural challenges. We are delighted that a company like Siroyan, who is redefining existing boundaries, has chosen CoSy as its preferred compiler development environment".

Siroyan has designed an VLIW-based Scalable Integrated Processor architecture - codenamed OPUS - that combines RISC and DSP elements, making it ideal for such demanding consumer-orientated applications as next-generation 3G mobile and internet connectivity, digital TV and digital video broadcasting. The Company will deliver the product as a softcore, codenamed RUBICON, which eliminates many of the process problems associated with the conventional hardcore approach. Siroyan calls its approach SIP², a combination of the unique Scalable Integrated Processor solution with a Semiconductor Intellectual Property delivery model.