NEC Electronics launches high-performance processor familyTokyo 11 June 2001 Delivering on its promise to provide high-performance processors for the embedded market, NEC Corporation and its semiconductor affiliates in the United States, NEC Electronics Inc., and Europe, NEC Electronics (Europe) GmbH, have expanded the 64-bit MIPSR RISC product offering with the VR5500, a microprocessor developed using NEC's new highly flexible and scalable VR5500 processor architecture. The initial device in a new product family, the VR5500 processor delivers 603 million instructions per second (MIPS) at 300 MHz, achieving one of the highest MIPS per MHz ratios in the industry. This performance is key for designers in the digital consumer, networking and storage markets where extremely high amounts of data must be processed simultaneously and quickly. NEC developed the new VR5500 architecture for scalable performance, enabling the development of future versions of standalone processors with speeds up to 800 MHz.
The flexibility of the architecture will enable NEC to develop a wide range of integrated solutions for various target applications. As a demonstration of these integration capabilities, NEC provided a technology overview for a future integrated product targeting network routers and switches and imaging and storage applications. This integrated processor will be developed using a 400 MHz VR5500 core with unified L2 cache integrated on-chip. Additionally, the single-chip solution will feature an integrated DRAM controller, PCI-X bridge and 10/100 base dual-mode Ethernet MAC. "The VR5500 architecture was developed by a highly focused internal development team," said Karl Auker, assistant general manager for the VR Series Microprocessor Strategic Business Unit, NEC Electronics. "The resulting product family leverages the core technology of our VR Series while providing even greater performance and flexibility for our customers developing high-performance applications such as network storage products and advanced set-top boxes. In addition, the scalability of this architecture represents exciting possibilities for this year and beyond as we develop products with greater levels of performance and integration to address the requirements of future embedded consumer and networking applications." Key to the VR5500 processor is its two-way superscalar micro-architecture featuring dual instruction issue, out-of-order execution and a ten stage decoupled superpipeline. The architecture contains six independent execution units, including two integer units, two floating-point units (FPU), a nonblocking load/store unit and a branch unit. The superpipeline includes a decoupled structure for more efficient processing and higher frequency implementation. This design provides nine stages operating at up to 400 MHz, and enables the execution of multiple instructions faster and more efficiently. To maximise the instructions issued and executed per cycle, the architecture supports 16 renaming registers and out-of-order execution.
The processor's 64-bit system bus supports speeds up to 133 MHz and also provides an optional 32-bit mode to enable more cost-effective system solutions. This micro-architecture delivers over 603 Dhrystone 2.1 MIPS and up to 150 million floating operations per second (MFLOPS) at 300 MHz. NEC's VR5500 family also features a new detachable execution unit architecture. This feature enables one FPU to be easily replaced with an application-specific coprocessor offering an unprecedented level of flexibility for future solutions that may require higher-performance digital signal processing, floating-point operation and/or other specific functions to be performed. The VR5500's design flexibility is further enhanced by the architecture's built-in debugging mode, which allows direct access to the core's execute instructions. The processor's 32 KB instruction and 32 KB data caches offer faster access to frequently used operations and data. The two-way set associative caches are nonblocking and support cache line locking. Write-back and write-through protocols are also supported. The VR5500's 1.5-volt core operation and 3.3-volt I/O operation, in combination with the high performance of the VR5500, make this device ideal for high-performance, power-efficient applications. The VR5500 architecture implements an enhanced version of the MIPS-IV instruction set architecture (ISA). Extensions to the ISA include three-operand multiply instructions and integer multiply-add instructions to benefit digital signal processing (DSP) applications. In addition, 32-/64-bit rotate and count leading 1/0 instructions were included to support printing and imaging applications. The VR5500 architecture is software-compatible with NEC's VR5000TM and VR5432TM products, as well as other MIPS-IV ISA compatible processors, providing an easy upgrade path. As a member of NEC's widely used VR SeriesTM processors, the new VR5500 microprocessor was developed by NEC using its 0.13-micron process technology. The processor includes enhanced JTAG and N-wire/N-trace support for nonintrusive debugging support. The VR5500 is compatible with major operating systems, including VxWorks, Linux and Windows CE, as well as software compilers from companies such as Algorithmics Ltd., Apogee Software Inc. and Green Hills Software Inc. Also presented by NEC was a companion chip to the VR5500, the VRC5477 memory and PCI system controller. A variety of VR5500-compatible controller chips from third-party vendors will also be available.
Ad Emmen |
 |