Increased speed of Pact reconfigurable parallel computing coprocessorSanta Clara 10 September 2001 PACT Corporation announced the implementation of a new set of design rules and processes for the company's eXtreme Processor Platform (XPP). XPP is deployed as a licensable IP (Intellectual Property) core for incorporation within SOC or DSP designs used in markets such as 2.5G+ base stations, mobile telephones and other devices requiring fully reconfigurable, massively parallel processing capabilities with minimum power requirements and maximum scalability.
XPP utilizes a massively parallel 'virtual ASIC' array of PAEs (Processing
Array Elements, made up of individual Arithmetic Logic Units) that can be
reconfigured on the fly, erased and rebuilt with virtually zero latency.
These virtual ASICs can also execute, be modified, or erased fully in parallel
of one another, or even with data interchange, across the array -- all the
while being fully controlled via a unique configuration manager that insulates
timing and data-dependency issues from the programmer or designer.
The core is tailored to meet the exponentially growing demands for
bandwidth and performance: benchmarks on the company's XPU-128 sample chip
have proven it to be the world's fastest 32-bit design. The core enables
efficient reconfiguration strategies, which can be performed in parallel for
the processing of data to achieve the highest possible application performance
-- equal to 50,000 MIPS or the equivalent of 80 Pentium 4 chips running in
parallel at 1.3 GHz, based on the initial 100 MHz clock speed of the core.
Using the LSI Logic (Milpitas, CA) .18 geometry ASIC Library has enabled
PACT to increase the clock speed of the core by 33% to 150 MHz+, while
simultaneously reducing the die size requirements for each individual PAE in
the XPP core. The power consumption for typical DSP algorithms running on XPP
is between 0.15W and 1.5W at the new clock frequency of 150 MHz. Using less
than 10% of the power draw of leading DSP designs, XPP enables new benchmarks
of flexibility and performance in silicon/software design and implementation.
To put this into perspective -- an array of 80, 24-bit PAEs especially
adapted to wireless applications such as CDMA, Software Defined Radio, 802.11b
and others can now achieve a performance of 12,000 24-bit MegaMACs / sec. or
24,000 12-bit MegaMACs / sec., with a total array size of 64mm(square). For
implementation as a high-performance workstation coprocessor using 128, 32-bit
PAEs now require an array size of 128mm(square), delivering a performance of
up to 76,800 32-bit MIPS or 307,200 8-bit MIPS.
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