Thomas Sterling explained that in the past processor architectures have used limited arithmetic logic function units on semiconductor dies dominated by caches and control elements. The aim was to achieve high utilization of those function units. This created an imbalance causing a gap between traditional architectures and alternative strategies.

The dominant issue in HPC is power consumption since it increases unfavourably with the now galoping speed of clock rate growth. Designing larger microprocessor architectures and as such make available more device transistors through a reduced feature size is no longer an option.

One of the new strategies therefore is multicore, the integration of more than one microprocessor core on a single semiconductor die. The power is being distributed over the number of cores thus proportionally increasing the overall number of functional units on one single die. Currently, industry is focusing on dual cores but in the near future this will be extended to four and even more cores, acoording to the speaker. The cores are interconntected in different ways but a much used approach is to share an on-chip L3 cache while keeping the L1 and L2 caches private to each core. Sometimes even full cache coherence is being offered among the caches of all cores on the die.

A famous example of multicore technology is the IBM BlueGene/L system which has taken over the first place in the TOP 500 list from the Earth Simulator last November and this with only one quarter of the machine installed. Each processor chip of the BlueGene/L has two processor cores with 64K nodes of this type, noted Mr. Sterling. He also added that multicore technology has migrated to the more widely available commodity clusters and named Intel as an exampble of a company that is coming out with its own multicore chips.

An alternative for putting many functional units on a single chip are ALU arrays. These are structures of function units interconnected and managed in many ways. Contrary to the earlier special purpose systems based on systolic structures, ALU arrays are programmable, explained Thomas Sterling. As a typical example which speaks to the imagination, the speaker cited the IBM Cell architecture developed initially for Sony to be employed in the next generation Playstation 3 game machine. The system's new chip will deliver over 200 Gflops 32-bit peak performance. It comprises a number of interconnected processors on a single chip and supports high bandwidth off chip to external memory. The speaker hoped that this technology will be applied to a broader range of high end computing purposes.

Passing to the evolution in programming languages, Thomas Sterling mentioned that all of MPI-2 is now available from different sources. The freely available and brandnew MPICH2 provides one-sided (Put/Get) routines and offers a beta-test version which is fully thread safe meaning that any thread may make any MPI call at any time. Programmers are preparing a modified version of MPI, OpenMPI, that incorporates advanced mechanisms for high reliability, the speaker announced.

As far as parallel programming of large systems is concerned, promising tools are Co-Array Fortran and UPC.

A recent advance is the merging of Co-Array Fortran semantics for array partitioning into the new standard for Fortran 08, explained Mr. Sterling. Other results in language development are delivered by by IBM, Sun Microsystems, and Cray Inc.

The speaker considered the Cray language, known as Chapel, as the state-of-the-art in languages for High End Computing Systems because it has a focus on productivity, combining the goal of a high-level programming abstraction with that of the best possible target code performance. Multithreading, locality-awareness, object-orientation, and generic programming are the four key areas of language technology used in the Chapel design. The IBM language is called X10 and the Sun language is called Fortress, as the speaker noted.

Thomas Sterling also addressed a number of other topics which have characterised HPC in the past year. As such, NASA has installed the by now well known "Constellation” class computer, developed by SGI. Sandia has deployed the Red Storm MPP comprising AMD Opteron processors while Cray is marketing a commercial version of this very system, known as XT3, which is implemented at both Oak Ridge National Labs and Pittsburg Supercomputer Center.

The speaker insisted on the increasing use of Grid technology for applications in academia, government, and industry in Asia, Europe, and North and South America. Myrinet and Gigabit Ethernet have succeeded in making Infiniband slowly penetrate the domain of high performance computer networking. In turn, Linux is growing in its dominance of cluster computing being the single most widely used operating system in the field of high end computing. Thomas Sterling concluded by indicating that the aggregate performance of all the systems on the Top 500 list for the first time has topped 1 Petaflops. Surely, this will not be the last time.

We did not quit get the sparkling presentation that Sterling did give in this report: although the facts are there, the enthousiasm, jokes and onliners are missing. A reason to go to ISC2006. Because, then Sterling will give his yearly update for the third time. If we cannot call it a tradition by then...