Until this moment we have been doing fine as far as supercomputer power efficiencies were concerned between 1997 and 2005. Alain Gara cited several examples including the Asci White Power 3, the Asci Q, the Earth Simulator, Columbia, BlueGene/L.

However, CMOS scaling is breaking down and we are already down to atoms causing industry to quickly arrive at the natural limitation imposed by physics. Indeed, if we consider the gate oxide in a CMOS transistor, having the smallest dimensions possible today, we have to assume that only 1 atom shows high "defects” on each surrounding silicon layer. For a modern "scaled” oxide of 6 atoms thick, this means that a 33% variability is induced. But Alain Gara explained that the bad news is that defects on one single atom can cause a local current leakage of 10 to 100 times higher than the average value. We definitely have a problem in the reliability department since oxides scaled below ~9 angstroms are too "leaky” and thus become unreliable.

On the other hand, how does one know that classical CMOS scaliing is really dead, the speakers asked themselves. Why would it be necessary to deviate from an "ideal" way of scaling? Well, you can reach additional performance at higher voltages. Remains the unacceptable gate leakage and the loss of reliability. So what is the consequence of this deviation? Engineers are able to achieve a dramatic rise in power density and this is good news.

Only, there is a restriction because power density is once again the key problem, according to the speaker. We have witnessed that the focus on single thread performance has resulted in a power inefficient design when building supercomputers. This message has an important impact on system design for it means that close in no longer remotely good enough, as stated by Alain Gara.

So what exactly are the challenges. It has occurred that "stopping” the chip no longer reduces chip power. Engineers will have to literally "unplug" unused circuits. The software must become much more sophisticated to cope with selective shutdowns of processor assets. Experience has made it clear that scaling produces profoundly different results when attempting to "push" chip speeds.

The speaker gave an example in which the power consumption for the CPU and logic was reduced by 13 times dynamically under the control of the Linux kernel.

It seems that the supercomputer community is facing a paradigm shift. Innovation will overtake scaling because innovation in design now dominates the performance gains between the various system generations. This means that the so-called scheduled invention is currently the majority component in all technology plans, the speaker stated.

This will bring about a redirection in technology and architecture that is already happening at this very instant.

The speaker provided the following future perspective to the audience. A mitigation of many power issues will be possible if engineers are prepared to aggressively exploit parallelism. Special purpose machines may strongly differentiate. The single thread performance constraints and expectations will drive much of the commercial direction. This will no doubt add a severe constraint to commercial system evolution. Still, innovation at the architectural and technology levels is critical.

The speaker assured that without any innovation there is trouble ahead because if we scale the current peak performance numbers for various architectures then we will allow the system peak to double every 18 months.

Therefore, close collaboration on high end systems with various partners will be paramount, according to Alain Gara. Parallelism is currently available and being exploited. Although it remains important, there should be less emphasis on single thread performance. Users are accustomed to leveraging "unique" hardware if there is value but a detailed analysis is necessary based on real applications.

The speaker is convinced that power reduction is achievable. The technology has been "over-leveraged" in the past years leaving significant room for power reduction. However, the power reduction has to be accompanied by system usability. Node architecture and a balanced network solution have to go hand in hand. Latency promises to be the biggest challenge for the future of networks. An increased parallelism will drive the messages sizes down and will stress the latencies.

If we want the change of direction to be successful, we will have to require hardware, compilers, middleware and programming model changes and some of these are likely to be discontinuous with respect to current practice. The speakers warned that exploring the architectural space will be expensive meaning that the commitment of industry and government are necessary for a positive progress.

The speaker ended his talk by stating that the technology disruption will require partners who know application characteristics and can help with performance modelling. As a result, the new approach must have broad application drivers and should be aggressive enough to be able to strongly differentiate while still being practical.

Alain Gara admitted that this can be a difficult line to walk. The system must be usable. in any case, the value of ideas and the approach will ultimately be decided by the various partners and other customers. An active engagement, strong collaboration and feedback are essential.