"Multi-core and heterogeneous architectures are creating a sea change in high performance computing", stated John Gustafson, ClearSpeed CTO for HPC. "To achieve the full potential of these new approaches, software must be developed or modified to exploit both data parallelism and thread parallelism. ClearSpeed's architecture and tools allow developers to take the easier path of data parallelism first by using well-established vector operations initially, then dealing with the additional complexity of thread-level parallelism as the second stage of the journey."

ClearSpeed acceleration can be achieved through a "plug and play" approach with BLAS and LAPACK standard libraries or by adapting or developing application code with the help of the ClearSpeed SDK. Applications that have already been shown to benefit from ClearSpeed acceleration range from molecular modelling codes, such as Amber 9 and the Bristol University Docking Engine (Bude), to financial applications based on Monte Carlo simulation. Standard toolkits supporting ClearSpeed acceleration include NAG, Wolfram Mathematica, and Interactive Supercomputing Corporation's Star-P.

Performance comparisons based on Monte Carlo benchmark code for European Option pricing provided by a major international bank showed up to 20 times performance speedup using a ClearSpeed Advance accelerator compared with an industry server. The use of multiple Advance accelerators in the system delivered up to 100 times performance speed-up.

The SDK package consists of CSXL, ClearSpeed's acceleration libraries that provide core linear algebra routines for matrix multiplication, ClearSpeed Vector Math Library and Random Number Generator Library, which support additional functionality, such as Monte Carlo simulation for option pricing in the financial services industry. Additionally, the SDK contains the ClearSpeed Visual Profiler toolset which provides insight at every level of the system, including the interactions between multiple host processors and one or more ClearSpeed Advance accelerator boards. By delivering a consistent visual representation across the entire system, it provides the easiest path to develop code that will perform optimally in today’s multi-core and heterogeneous accelerated systems.

Developers creating or adapting applications to efficiently exploit the inevitable heterogeneous multi-core future can start today on the ClearSpeed hardware and software platform. At ISC'07, developers will be able to view live demonstrations of ClearSpeed software and the acceleration of financial and scientific applications at ClearSpeed's booth, #C32, on Wednesday, June 27 from 9 a.m. – 6.45 p.m. and on Thursday, June 28 from 9 a.m. – 7 p.m.

Additionally, developers are invited to the ClearSpeed speaker session about ClearSpeed's software:

• Thursday, June 28, 10 - 11 a.m. - John Gustafson, CTO of HPC, and Simon McIntosh-Smith will present on "Using Accelerators to Escape the Shackles of 20th Century Software"