Shalf starts his presentaion with noticing that 15 years of exponential clock rate growth has ended. But Moore's Law continues to be true: the number of transistors on a chip still grows. Then how do we use all of those to keep performance increasing at historical rates? Industry response has been to put more computing cores on a single chip. We see that today the number of cores per chip doubles every 18 months instead of the clock frequency.

There are several reasons for this multi-core approach. One is the power limits for leading edge chips. They tend to get very hot. The Intel Tejas Pentium 4 was cancelled due to power issues, said Shalf. Also the yield on leading edge processers has been dropping dramatically. IBM reports only 10-20% good chips of the 8-processor Cell. Also the chips tend to become so complex that managing the design becomes almost impossible.

The design trend is towards smaller cores that are not so fast but much more power efficient. Typically the small cores are about 1/3 or 1/10 the effecieny of a larger core, but you can pack 100x as much cores on a single chip and consume only 1/20 of the power. As a comparison, Shalf gives the example of the IBM Power 5 chip: 389mm^2, with a power consumption of 120W and a clock frequency of 1900MHz. The Tensilica DP that is used in cell phones is only 0.8mm^2, consumes 0.09W at a clock frequency of 600MHz. So we can expect a complete new type of processing core too. It is not only just packaging more and more advanced cores on a single chip.

The architecture design goal in supercomputing is no longer the ultimate sustained-to-peak performance, as is commonly thought today, but should be performance/watt. Shalf shows that building an exaflop/s supercomputer with current technology, would result in a 130 MWatt power consumption, or a power bill for over 100 million euro per year.

So HPC architects must change their view on how a supercomputer should be built. They also must understand application requirements to be able to design the next generation architecture.

There are two types of "more core" chip design. There is multi-core. Basically this is taking a fast processor core and doubling the number of cores on a chip every 18 months. The other one is called many-core. This uses simplified cores with shorter pipelines, lower clock frequencies and in-order processing. These start at 100s of cores and also double in number every 18 months.

Eventually everything will converge towards many-core, Shalf believes, if we can figure out how to program it.

It is not longer only the HPC industry who is doing parallel processing. It is the entire computing industry that is betting its future on parallelism. According to Shalf, also the innovation flow has been reversed. Innovation will be trickling up from consumer applications to HPC. Consumer application developers know more about computational/power efficiency than HPC developers and more about cost-effectiveness. HPC is not longer in the driver seat. In the future even your toaster will be running parallel applications on many-core processors, he predicts.

But a major problem is that nobody knows how to program these systems, there is no software solution in place, neither in consumer electronics.

Shalf sees three possible failure modes for the multi-core revolution. The first is system balance. There is a concern that memory and interconnect performance will ultimately cap multi-core performance. The second one is reliability: More "moving parts" in these systems means there is more opportunity for failures. The third is programmability. How can we program systems with a million or more cores?

According to Shalf, a key limiting factor is software infrastructure. Current software is designed with implicit assumption of smaller concurrency, say hundreds or thousands of processors. Millions of processors were not part of the original design assumptions. This requires fundamental re-thinking of the Operating System and mathematical library design assumptions.

In application programming, models like MPI, or SMP will not do the job, says Shalf. But with "transactional memory", the silver bullet is already in our hands. This could be implemented in hardware.

In addition, advanced compiler technology is needed. Probably this will involve compilers that optimise by running trial and simulation versions of the programme first. On a higher level, large community frameworks like Chombo, Cactus, SIERRA, and UPIC, will hide the complexity for the end-user.

Shalf expects the next 3-5 years we will see new hardware and associated software designs to explore new many-core architectures. Application software development will even take longer.

In this multi-core exploration, HPC is not alone or even at the forefront: it is the complete computer industry that is moving into this direction.