As usual, Professor Dr. Hans Meuer and his team (family) from the University of Mannheim put up a fine vendor exhibition, a collection of stimulating presentations and delivered a seamless conference in the beautiful historical city of Dresden. The main sponsor this year was Microsoft, a vendor with an aspiration to capture a big share of the parallel and HPC software market. The Microsoft sponsored Saxon night at the Albrechtsberg Palace was exquisite.

ISC2007 provided an opportunity for vendors to peddle their products and share with us their plans for products expected in the near future. Readers have access to many articles in the live issues of this publication from ISC. As keynote speaker Burton Smith from Microsoft has been quoted extensively from this conference. The next two paragraphs highlight Burton's main ideas for the new parallel languages needed, in the multi-core world.

In parallel languages there are (at least) two promising approaches: Functional programming and atomic memory transactions. Neither is completely satisfactory by itself. Functional programmes don't allow mutable state. Transactional programmes implement dependence awkwardly. Data base applications show the synergy of the two ideas. SQL is a "mostly functional" language while transactions allow updates with atomicity and isolation. Many people think functional languages are inefficient. Sisal and NESL are excellent counterexamples of that view as both competed strongly with Fortran on Cray systems. Others believe the same is true of memory transactions, but this remains to be seen as we have only begun to optimise.

We need to support multiple programming styles, functional and transactional, data parallel and task parallel, message passing and shared memory, declarative and imperative, implicit and explicit. We may need several languages to accomplish this, similar to the use of multiple languages today with a helpful language interoperability bridge (e.g. .NET). It is essential that parallelism be exposed to the compiler so that the compiler can adapt it to the target system. It is also essential that locality be exposed to the compiler and for the same reason.

The only other thing I can say is that with the advent of multi-core and future many-core chips, Microsoft is aware that producing parallel software has become core for their future business. This means that their entry is for real.

Several hardware vendors highlighted how they intend to deliver the productivity promise and sustained 1Petaflops by 2010 and beyond. These included Cray with their Cascade, IBM with their precursor Power6 and the Blue Gene/P product lines leading to upgraded versions for Petaflop/s systems at a later date, as well as other vendors NEC, Fujitsu, Bull and Sun Microsystems with the 32 threads Niagara Chip, and so on. These companies have roadmaps heading for the Petaflop/s milestone.

The conference provided a broad range of talks. The "Geeks" embraced the multi-core revolution and are relishing the idea of having many-cores and as Thomas Sterling (LSU) expounded myriad-cores. Sterling found ample support from John Shalf (LBNL) who betrayed his enthusiasm with an audacious presentation title: "Overturning the conventional wisdom for the multi-core Era: Everything you know is wrong". I am wondering whether John reflected on the semantics of such a sweeping assertion. I leave it to the reader to decide, but as for myself some of what I know about multi-core could probably be wrong, not everything.

John went on to say that power efficiency motivates many-core design and made the case for using many-cores with a simplified instruction set and shorter pipelines. Being prone to a "geek" mentality John did not shy from the catching phrase: "In the old computer world: Innovation trickles down from High End Computing to the PC and consumer electronics. In the "New" world innovation trickles up from the PC and consumer electronics to HPC.

If only the world was that simple. The real issue is not about old and new, but rather of "good" ideas being adopted and then transferred to a different application domain. For example, in the 1980s innovation on the PC concerning human machine interfaces was transferred to the High End computers. At that time the emphasis of High End Computers such as the Cray-1, was on using its scarce resources for numerical calculations neglecting the human machine interface. As soon as the PCs arrived with easy to use interfaces, the high end user community demanded and soon got a better deal. Another example is in storage devices, where the developments were powered by the music industry and the technology was then taken up by the computer industry and HPC.

To be fair, John recognizes that latency tolerance and lack of software to exploit multi-core are key limiting factors. For me this talk effervesced with enthusiasm (always a good thing) about many-cores, but provided sparse practical solutions on how to overcome the difficulties. The multi-core Era can become a reality, but needs to ease the pain of this transition, for the long suffering application user. In the words of the Bard: "Between the ideal and reality stands the shadow..."

At this point a reality check is in order. The increasing demand, for higher performance, can no longer be achieved through Moore's law processor improvements and a one-size-fits-all, system mentality. HPC users are no longer getting the performance advances they need from microprocessors. Commercial response to Moore's law slowdown has been, to provide multi-core and promise many-core chips. These are general-purpose architectures, optimised for most widely used applications. But as it is widely recognized when scientific computing migrated to commodity platforms, interconnect speed, both in terms of bandwidth and latency, became the limiting factor on application performance and remains a bottleneck to this day.

The new mantra is that although multi-core commodity processors will deliver some improvement, exploiting parallelism through a variety of processor technologies using scalar, vector, multi-threading and hardware accelerators, e.g. FPGAs, GPUs ..., creates the greatest opportunity for application acceleration.

Near future supercomputing systems combine multiple processing architectures, into a single scalable system. Looking at it from the user point of view, one has the application programme, followed by a transparent interface, using libraries, tools, compilers, scheduling system management and a runtime system. The intention is to adapt the system to the application - not the application to the system.

As readers of this publication are aware, there are many challenges to be overcome, not least in memory and network subsystem capabilities as well as managing software complexity, on the way to the 1Petaflops productivity promise. In current architectures, processors are separated from memory, from which they fetch operand data to feed the arithmetic functional units. This is accentuated by the network latency, when servicing the many thousands of processors, required for the 1Petaflops system. Thus, delays tend to accumulate.

In practice scaling an SMP or cluster to such large numbers of processors required to achieve Petaflop/s is very difficult. Efficiency degrades sharply because of requirements for cache coherence and also from operating system jitters. The key task for system software, in heterogeneous systems, lies in scheduling strategies and other system functions that maximize the performance extracted from scarce system resources, notably the heterogeneous system's limited global system bandwidth. In other words, how one minimises and hides latency.

Thomas Sterling gave two talks: One on the HPC achievements and impact since last year and the other on multi-core, the next Moore's Law. He used as an exemplar the IBM Blue Gene/L and its successor the Blue Gene/P illustrating the emergence of multi-core processors on one die, used to stem the power consumption explosion. For new systems the Flops/Watt metric is expected to become as important as Flops/Dollar metric became in the 1990s.

Thomas pointed out that multi-core exploits the extra real-estate due to increased circuit density, increases functional units per chip (spatial efficiency), which in turn limits energy consumption per operation. Multi-core would improve on Moore's Law in respect to peak performance, but pins will grow much slower. Exemplar is the Cell processor, 0.25Teraflops on a chip (9-ways). To address the multi-core challenge one needs more than an SMP on a chip. One needs parcels for latency hiding, destination locale split phase and message driven transaction computing. Most important, the new system delivers latency hiding. Latency hiding with parcels will deliver 1 to 2 orders of magnitude performance benefits.

Thomas then described work at LSU where his team is currently exploring key challenges of a new class of computer architecture to confront efficiency, scalability, power and reliability. This requires a paradigm shift of execution and programming models. There is a desperate need for intrinsic latency hiding mechanisms to be incorporated in the infrastructure of programming and runtime resource management.

He went on to say: "We are developing a new model for computing called 'ParalleX', extending our earlier work in processor in memory (PIM), and combining these with new work in static dataflow to provide a new class of architecture that adaptively responds to variations in temporal locality. The short-term impact is that the execution model has a spin-off of a programming methodology that can operate on conventional architecture. It should improve latency hiding and scalability."

Jose Duato, from the Technical University of Valencia, gave an excellent keynote presentation describing the pros and cons of systems based on commodity chips, current trends and synergies, feasible future system architectures and identified interconnect as the key subsystem.

He started by explaining that research in academia usually focuses on narrow topics e.g. processor micro-architecture, memory hierarchy, cache coherence protocols, interconnection networks, and so on. Even when radically new solutions are proposed e.g. a cost-effective fully adaptive routing algorithm, those solutions only improve a subset of the system and do not eliminate the inefficiencies that are a direct consequence of the system architecture, which may not be globally optimal. This means too many resources or power budget are devoted to improve a component that is not the system bottleneck. A global system view is required even when addressing problems in a particular subsystem.

When looking at computer systems from a global perspective, researchers start (or should start) by looking at application requirements, but there is a fundamental flaw in this approach: Existing applications were designed for existing computer systems and new computer systems are designed to run existing benchmarks faster. In this global optimisation process, practitioners neglect the opportunity to replace the existing programming model and style and may end up proposing techniques to recover parallelism that has been lost due to previous optimisations.

In some proposed solutions applications are written in such a way that most parallelism is lost, having to use speculation techniques to recover it. The proposed techniques tend to increase power consumption. A more efficient approach is to redesign the inner programme loops, transmitting each value after computing it by specifying it in the programme and let an optimised implementation of MPI to decide whether each value should be immediately transmitted or should be packed together with other values into a single message to reduce the communication start-up overhead. The correct solution is a truly global view.

The heat dissipation wall forced microprocessor manufacturers to move to multi-core chips needing much less power consumption for the same peak computing power. Manufacturers are increasing the number of cores per chip but at a slower frequency rate. At least one core should be as fast as the fastest core in the previous generation chip. Many users do not know what to do with additional cores (beyond running anti-virus and firewall). The current trend will soon face the memory bandwidth wall problem on how to feed the cores. This is further aggravated when running applications that do not share data (e.g. multiple virtual servers) and/or when including the graphics accelerator on the same chip.

Necessity is the mother of invention. Accelerators, which can execute repetitive compute-intensive functions much faster than host processors are being utilised. Different flavours: GPU-based accelerators, FPGA-based accelerators, DSP-based accelerators are available, but these are not good for code fragments with high memory bandwidth requirements, unless the accelerator implements a large and fast local memory (e.g. graphics cards). They are nevertheless becoming popular due to the availability of compilers and programming tools.

With multi-core chips it is no longer possible to exploit parallelism in an automatic mode: Applications need to be multithreaded. It has been quite easy to convince desktop and laptop users that a second core is beneficial even for running single-thread applications. Perhaps one can run anti-virus and firewall on the second core, but what does one do with four cores?

Simpler programming models are likely to become much more widespread than more sophisticated ones (e.g. shared memory vs. message passing). Not hiding architectural details from application developers may make it more difficult to accept a given architecture. Observe the XBox 360 vs. PlayStation 3 battle.

Looking at synergies, mass-market applications that require more computing power (e.g. video games) are forcing application developers toward parallel programming. The numbers of programmers able to develop multi-threaded applications are likely to increase at a fast pace during the next few years. Most of these application developers will become familiar with shared-memory models, but not so much with message passing. This trend is likely to make parallel programming more popular, but shared-memory machines are likely to be preferred over current clusters.

Processor multi-cores have become commodity components. Chip architecture and system architecture have become much more relevant. Many characteristics such as how many cores and how are they interconnected (i.e. on-chip networks); homogeneous vs. heterogeneous cores; cache hierarchy and how many levels, private vs. shared; pin bandwidth constraints; memory organization, i.e. local vs. shared; hardware coherence vs. software coherence vs. coherence domains vs. non-coherent. Network interfaces and where do we attach them. As for storage we need to decide from traditional hard disks vs. solid-state disks vs. non-volatile memory (i.e. FLASH).

As for memory subsystems, large-scale cc-NUMA architectures are based on the idea of using physically distributed, logically shared memory. Caches are mandatory to deliver good performance and keeping them coherent in large systems is a nightmare. Cc-NUMA architectures are very expensive and not very scalable. Non-coherent shared-memory architectures as well as shared-memory architectures with multiple coherence domains are feasible. Accelerators can play a vital role in increasing computing power and reducing power consumption. Feasible, scalable, flexible and cost-effective approach for future systems is a global address space, not necessarily coherent, where each page has configurable semantics (coherent, non-coherent, transactional).

The most difficult task when developing multithreaded applications using transactional memory is making sure that the programme works (e.g. deadlocks may occur when combining correct code fragments). Transactional memory is a concurrency control mechanism for controlling access to shared memory. A transaction is a piece of code that executes a series of reads and writes to shared memory, which logically occur at a single instant in time, and are typically implemented in a lock-free way.

Transactional memory is optimistic: every thread completes its modifications to shared memory without regard for what other threads might be doing, recording every read and write that it makes in a log, which are validated in the commit stage. Implementing part of the system memory, as transactional memory could be the solution for storing shared data in parallel applications while simplifying programming.

To recap the use of commodity components has been the key to deliver tremendous affordable computing power. Architectures based on current commodity components have intrinsic limitations that prevent efficient exploitation of parallelism. Current multi-core trends will force the rapid expansion of shared-memory parallel programming. Computer industry should use this unique opportunity to design scalable, cost-effective shared-memory architectures.

Low-latency, high-bandwidth interconnects are the key subsystem to enable the design of scalable shared-memory architectures. Several efficient solutions exist for different subsystems including interconnects. What remains to be done is finding the right combination of components that will enable those high-performance architectures to be implemented at low cost.

As Martin Luther King said: "I have a dream." Future architectures would be a series of standard modules defining coarse system functions such as compute cores, memories including transactional and their respective interconnects to memory and inter-chip networks. The compute cores would be heterogeneous including blank pieces of silicon, field programmable and populated by a processor designs taken from a library on demand, verified to optimally match the user application. The system would have globally addressable memory, but not necessarily globally coherent. A new standard parallel programming paradigm, functional and transactional but at a higher abstraction is universally adopted and is in common use. The age of the "Soft Computer" will then be upon us.

I leave you with an Albert Einstein maxim on simplification: "All should be as simple as possible, but not simpler."