Tera completes design of new MTA chip
Seattle 27 Jul 99 Tera completed the development phase of its CMOS MultiThreaded Architecture (MTA) microprocessor chip. The chip's design has been completed and sent to the fabricator, Taiwan Semiconductor Manufacturing Company. Delivery of the new 64-bit microprocessor parts is expected later this quarter.
Jerry Loe, Vice President Hardware Engineering said, "We plan to integrate CMOS technology into all aspects of the Tera MTA hardware design over time. This technology will greatly reduce our manufacturing costs and improve reliability. For example, a single CMOS processor chip replaces 24 chips in the current design."
"The design challenges presented in implementing an MTA microprocessor in CMOS were formidable," Loe said. "Conventional microprocessors perform arithmetic at one speed but transfer information to and from the chip at a much slower speed, typically one third as fast or less. The input/output on Tera's new chip is designed to work at the same high speed, nominally 300 MHz, as the MTA processor. Consequently, an MTA microprocessor is designed to support dramatically higher computing speeds than current processors. Benchmarks of Tera's MTA systems indicate that its existing processor design can typically outperform today's microprocessors by factors of three to six. Tera's advantage is further magnified in multiprocessor systems because of MTA's better applications scalability."