Tera post third Quarter 1999 results

Seattle 28 Oct 99 Tera Computer Company reported results for the third quarter ended September 30, 1999. The company reported a third quarter net loss of $7.5 million on revenues of $850,000 compared with a net loss of $4.2 million, on $232,000 in the year-ago quarter. In addition, the company today announced initial positive test results for two types of CMOS asics, an MTA processor chip and memory bank controller, the design of which had been taped-out and sent to the chip fabricator in July, 1999.

This is a crucial step in the evolution of Tera's Multithreaded Architecture (MTA) high performance computers, as it will reduce costs and greatly improve testing, manufacturability and reliability. Accordingly, Tera is taking a non-cash reserve charge of approximately $6.4 million in the third quarter against its inventory of gallium arsenide processors, integrated circuits and associated components and parts accumulated over the past year. The Company plans to begin phasing out gallium arsenide components with CMOS chips - ahead of schedule -- beginning with production of the MTA-16 system.

The recent quarter's results also reflected approximately $2.7 million in costs comprised of payments to Cadence Design for CMOS engineering and design services and private placement related expenses. Of the 1999 third quarter revenue, $814,000 was from the sale of the four-processor upgrade MTA system to the San Diego Supercomputer Center; additional revenue for this sale of $300,000 will be recognized upon Congressional authorization of funds, expected in the fourth quarter. Including the inventory reserve charge, the net loss for the third quarter was $13.9 million, or per share.

"The third quarter was highlighted by the achievement of three important milestones," said Jim Rottsolk, Tera president and chief executive officer. "First, the San Diego Supercomputer Center (SDSC) accepted our MTA-8, which is currently producing application test results exceeding our expectations. Although we doubled the size of the system at SDSC, and the acceptance criteria were the most stringent so far, the actual acceptance process was the smoothest to date.

"Second, we made a major step toward commercialization with the July tape-out and current testing of our CMOS processor and memory control chips," Rottsolk said. "We received the chips back from Taiwan Semiconductor on schedule and had excellent initial yield and packaging results. The testing of the packaged parts has been better than anticipated and the initial testing results have confirmed our view that shipments to our customers in 2000 will be with CMOS components. As a result, we no longer expect to utilize the majority of our gallium arsenide inventory and have recorded the non-cash charge."

"Third, and most important," Rottsolk added, "We expect to ship an MTA-16 to SDSC, on track with our stated goal to double the number of processors in the MTA every six months. Furthermore, we are excited about reaching this milestone as I am confident that the MTA-16, with CMOS components, will mark Tera's entrance into full scale commercialization and sales in year 2000."

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